// include file used to hide some weird code from the students

// dip switches are "on" (connected to GND) when down
wire [31:1] sw = swi; 

wire reset = ~sw[3];

wire show_stack = (onda=='h3FF) ;  // Indicates that we are
    // acessing primary memory displaying stack contents.

// ************ Clock signal ******************
// Create clock signal free of glitches
// using the bipolar switch or an external clock signal.
// The selection between clocks has to be glitch free, too.

// slow down the external clock signal 8000 times
reg [12:0] slow;
reg slowclock;
always @(posedge clock) begin
    slow <= slow + 1;
    slowclock <= (slow > sw[28:16]);
end

// switch selects between fast and slow clock
wire sysclock = sw[1] ? clock : slowclock ;

reg pushing;
always @(negedge sysclock) pushing <= ~pushing;

reg clkselect;

// The two basic signals of the clock generator
// are 'push' and 'pull'. The clock signal as
// well as the 'WE' signal are derived from them.
// 'push' and 'pull' may come from either the bipolar switch
// or from the 555 oscillator.

wire push = clkselect ?  pushing & sysclock : ~bip[0];
wire pull = clkselect ? ~pushing & sysclock : ~bip[1]; 

reg clk, clkn;
always @(push or pull)
    if (pull)
      begin
        clk <= 0;
        clkn <= 1;
      end
    else if (push & ~show_stack)  // Avoid clock going active while
           begin                  // displaying stack.
             clk <= 1;
             clkn <= 0;
           end
    else begin
           clk <= clk;
           clkn <= clkn;
         end

// clock signal selection becomes active only by switching
// the bipolar switch
wire select = bip[0] & bip[1];
always @(posedge select or negedge reset)
  if (!reset) clkselect <= 0;
  else clkselect <= sw[2];

wire true = onda || sw[31:1] ; // dummy

assign led[64] = clk & true;  //avoid silly warnings using dummy